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System-Level Digital Design Synthesis | |
The following sources are recommended by a professor whose research specialty is system-level digital design. |
· Granacki, J., and Parker, A.C., "PHRAN-Span: a natural language interface for system specifications," in Proc. 24th Design Automation Conference, June 1987, 416-422.
· Gajski, D.D., Vahid, F., Narayan, S., and Gong, J., Specification and Design of Embedded Systems, Prentice Hall, 1994.
· Prakash, S., and Parker, A.C., "SOS: Synthesis of application specific heterogeneous multiprocessor systems," Journal of Parallel and Distributed Computing, 16, 338-351, Dec. 1992, reprinted in Readings in Hardware/Software Co-Design, edited by Giovanni de Micheli, Rolf Ernst, and Wayne Wolf. Morgan Kaufmann, 2001.
· Tirat-Gefen, Y.G., and Parker, A.C., "MEGA: An Approach to System-Level Design of Appliation Specific Heterogeneous Multiprocessors," Proc. of Heterogeneous Computing Workshop of the 1996 International Parallel Processing Symposium, pp. 105-117, 1996.
· Srivastava, M.B., Richards, B.C., and Broderson, R.W., "System level hardware module generation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3, 20, 1995.
· Kalavede, A., Pino, J.L., and Lee, E.A., "Managing complexity in heterogeneous system specification, simulation and synthesis," Proceedings of the International Conference on Acoustics, Speech and Signal Processing (ICASSP), May, 1995.
· Harel, D., "Statecharts: A visual formalism for complex systems," Science of Computer Programming, 8, 231-274, June 1987.
· Vahid, F., Narayan, S., and Gajski, D.D., "SpecCharts: A VHDL front-end for embedded systems," IEEE Trans. on CAD, 14, 694, 1995.
· Wadekar, S.A., and Parker, A.C., "Accuracy sensitive word-length selection for algorithm optimization," in Proceedings of the International Conference on Circuit Design (ICCD), 1998, 54.
· Wadekar, S.A., and Parker, A.C., "Algorithm-level verification of arithmetic-intensive application-specific hardware designs for computation accuracy," in Digest Third International High Level Design Validation and Test Workshop, 1998.
· Gupta, P., Chen, C.T., DeSouza-Batista, J.C., and Parker, A.C., "Experience with image compression chip design using unified system construction tools," in Proceedings of the 31st Design Automation Conference, 1994.
· Cyre, W.R., Armstrong, J.R., and Honcharik, A.J., "Generating simulation models from natural language specifications," Simulation, 65, 239, 1995.
· Tanir, O., and Agarwal, V.K., "A specification-driven architectural design environment," Computer, 6, 26-35, 1995.
· de Jong, G., and Lin, B., "A communicating Petri net model for the design of concurrent asynchronous modules," ACM/IEEE Design Automation Conference, June 1994.
· Lagnese, E., and Thomas, D., "Architectural partitioning for system level synthesis of integrated circuits," IEEE Transactions on Computer-Aided Design, 10(7), 847-860, 1991.
· Vahid, F., A Survey of Behavioral-Level Partitioning Systems, Technical Report TR ICS 91-71, University of California, Irvine, 1991.
· Kucukcakar, K., and Parker, A.C., "Chop: a constraint-driven system-level partitioner," in Proceedings of the 28th Design Automation Conference, 1991, 514.
· Vahid, F., and Gajski, D.D., "Specification partitioning for system design," in Proceedings of the 29th Design Automation Conference, 1992.
· Parker, A.C., Chen, C.-T., and Gupta, P., "Unified system construction," in Proceedings of the SASIMI Conference, 1993.
· Bokhari, S.H., Assignment Problems in Parallel and Distributed Computing, Kluwer Academic Publishers, 1987.
· Stone, H.S., and Bokhari, S.H., "Control of distributed processes," Computer, 11, 97, 1978.
· Haddad, E.K., Optimal Load Allocation for Parallel and Distributed Processing, Technical Report TR 89-12, Department of Computer Science, Virginia Polytechnic Institute and State University, April 1989.
· Indurkhya, B., Stone, H.S., and Cheng, L.X., "Optimal partitioning of randomly generated distributed programs," IEEE Transactions on Software Engineering, SE-12, 483, 1986.
· Nicol, D.M., "Optimal partitioning of random programs across two processors," IEEE Transactions on Software Engineering, 15, 134, 1989.
· Lee, C.Y., Hwang, J.J., Chow, Y.C., and Anger, F.D., "Multiprocessor scheduling with interprocessor communication delays," Operations Research Letters, 7, 141, 1988.
· Tirat-Gefen, Y.G., Silva, D.C., and Parker, A.C., "Incorporating imprecise computation into system-level design of application-specific heterogeneous multiprocessors," in Proceedings of the 34th Design Automation Conference, 1997.
· DeSouza-Batista, J.C., and Parker, A.C., "Optimal Synthesis of Application Specific Heterogeneous Pipelined Multiprocessors," in Proceedings of the International Conference on Application-Specific Array Processors, 1994.
· Mehrotra, R., and Talukdar, S.N., Scheduling of Tasks for Distributed Processors, Technical Report DRC-18-68-84, Design Research Center, Carnegie-Mellon University, December 1984.
· Agrawal, R., and Jagadish, H.V., "Partitioning techniques for large-grained parallelism," IEEE Transactions on Computers, 37, 1627, 1988.
· Barthou, D., Gasperoni, F., and Schwiegelshon, U., "Allocating communication channels to parallel tasks," Environments and Tools for Parallel Scientific Computing, Elsevier Science Publishers, 1993, 275.
· Linsky, V.S., and Kornev, M.D., "Construction of optimum schedules for parallel processors," Engineering Cybernetics, 10, 506, 1972.
· Chu, W.W., Hollaway, L.J., and Efe, K., "Task allocation in distributed data processing," Computer, 13, 57, 1980.
· Prakash, S., Synthesis of Application-Specific Multiprocessor Systems, PhD Thesis, Department of Electrical Engineering and Systems, University of Southern California, January 1994.
· Hafer, L., and Parker, A., "Automated synthesis of digital hardware," IEEE Transactions on Computers, C-31, 93, 1981.
· Fernandez, E.B., and Bussel, B., "Bounds on the number of processors and time for multiprocessor optimal schedules," IEEE Transactions on Computers, C-22, 745, 1975.
· Garey, M.R., and Graham, R.L., "Bounds for multiprocessor scheduling with resource constraints," SIAM Journal of Computing, 4, 187, 1975.
· Jaffe, J.M., "Bounds on the scheduling of typed task systems," SIAM Journal of Computing, 9, 541, 1991.
· Gupta, R., and Zorian, Y., "Introducing core-based system design," IEEE Design and Test of Computers, Oct.-Dec., 15, 1997.
· Li, Y., and Wolf, W., "A task-level hierarchical memory model for system synthesis of multiprocessors," in Proceedings of the Design Automation Conference, 1997, 153.
· IEEE Design and Test of Computers, special issue on rapid prototyping, 13(3), 1996.
· Birmingham, W., and Siewiorek, D., "MICON: a single board computer synthesis tool," in Proceedings of the 21st Design Automation Conference, 1984.
· Chen, C-T, System-Level Design Techniques and Tools for Synthesis of Application-Specific Digital Systems, PhD Thesis, Department of Electrical Engineering and Systems, University of Southern California, January 1994.
· Heo, D.H., Ravikumar, C.P., Parker, A., "Rapid synthesis of multi-chip systems," in Proceedings of the 10th International Conference on VLSI Design, 1997, 62.
· Lee, E.A., and Bier, J.C., "Architectures for statically scheduled dataflow," Journal of Parallel and Distributed Computing, 10, 1990, 333-348.
· Gajski, D.D., Vahid, F., and Narayan, S. "A design methodology for system-specification refinement," in Proceedings of the European Design Automation Conference, 1994, 458.
· Renfors, M., and Neuvo, Y., "The maximum sampling rate of digital filters under hardware speed constraints," IEEE Transactions on Circuits and Systems, CAS-28, 196, 1981.
· Wang, D.J., and Hu, Y.H., "Multiprocessor implementation of real-time DSP algorithms," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3, 393, 1995.
· Gelabert, P.R., and Barnwell, T.P., "Optimal automatic periodic multiprocessor scheduler for fully specified flow graphs," IEEE Transactions on Signal Processing, 41, 858, 1993.
· Tirat-Gefen, Y.G., Theory and Practice in System-Level of Application Specific Heterogeneous Multiprocessors, Ph.D. Dissertation, Dept. of Electrical and Computer Engineering, University of Southern California, 1997.
· DeSouza-Batista, J.C., Potkonjak, M., and Parker, A.C., "Optimal ILP-based approach for throughput optimization using algorithm/architecture matching and retiming," in Proceedings of the 32nd Design Automation Conference, June 1995, 113-118.
· Verhauger, W.F., Multidimensional Periodic Scheduling, PhD Thesis, Eindhoven University of Technology, 1995.
· Passos, N.L., Sha, E.H., and Bass, S.C., "Optimizing DSP flow-graphs via schedule-based multidimensional retiming," IEEE Transaction on Signal Processing, 44, 150, 1996.
· Feng, D.T., and Shin, K.G., "Static allocation of periodic tasks with precedence constraints in distributed real-time systems," in Proceedings of the 9th International Conference of Distributed Computing, 1989, 190.
· Ramamritham, K., "Allocation and scheduling of precedence-related periodic tasks," IEEE Transactions on Parallel and Distributed Systems, 6, 1995.
· Ramamritham, K., Stankovic, J.A., and Shiah, P.F., "Efficient scheduling algorithms for real-time multiprocessors systems," IEEE Transaction on Parallel and Distributed Systems, 1, 184, 1990.
· Michalewicz, Z., Genetic Algorithms and Data Structures Equal Evolution Programs, Springer-Verlag, 1994.
· Hou, E.S.H, Ansari, N., and Ren, H., "A Genetic algorithm for multiprocessor scheduling," IEEE Transactions on Parallel and Distributed Systems, 5, 113, 1994.
· Wang, L., Siegel, H.J., and Roychowdhury, V.P., "A genetic-algorithm-based approach for task matching and scheduling in heterogeneous computing environments," in Proceedings of the Heterogeneous Computing Workshop, International Parallel Processing Symposium, 1996, 72.
· Ravikumar, C.P., and Gupta, A., "Genetic algorithm for mapping tasks onto a reconfigurable parallel processor," IEEE Proceedings in Computing Digital Technology, 142, 81, 1995.
· Liu, J.W.S., Lin, K.-J., Shih, W.-K., Yu, A.C.-S., Chung, J.-Y., and Zhao, W., "Algorithms for scheduling imprecise computations," IEEE Computer, 24, 58, 1991.
· Ho, K., Leung, J.Y-T., and Wei, W-D., Minimizing Maximum Weighted Error for Imprecise Computation Tasks, Technical Report UNL-CSE-92-017, Department of Computer Science and Engineering, University of Nebraska, 1992.
· Tirat-Gefen, Y.G., Silva, D.C., and Parker, A.C., "Incorporating imprecise computation into system-level design of application-specific heterogeneous multiprocessors," in Proceedings of the 34th. Design Automation Conference, 1997.
· Malcolm, D.G., Roseboom, J.H., Clark, C.E., and Fazar, W., Application of a technique for research and development program evaluation, Operations Research, 7, 646, 1959.
· Elmaghraby, S.E., "The theory of networks and management science: Part II," Management Science, 17, B. 54, 1970.
· Fulkerson, D.R., "Expected critical path lengths in pert networks," Operations Research, 10, 808, 1962.
· Robillard, P., and Trahan, M., "The completion time of PERT networks," Operations Research, 25, 15, 1977.
· Mehrotra, K., Chai, J., and Pillutla, S., A Study of Approximating the Moments of the Job Completion Time in PERT Networks, Technical Report, School of Computer and Information Science, Syracuse University, 1991.
· Kulkarni, V.G., and Adlakha, V.G., "Markov and Markov-regenerative PERT networks," Operations Research, 34, 769, 1986.
· Hagstrom, J.N., "Computing the probability distribution of project duration in a PERT network," Networks, 20, 231, 1990.
· Kamburowski, J., "An upper bound on the expected completion time of PERT networks," European Journal of Operational Research, 21, 206, 1985.
· Purushothaman, S., and Subrahmanyam, P.A., Reasoning about probabilistic behavior in concurrent systems, IEEE Transactions on Software Engineering, SE-13, 740, 1987.
· Thomasian, A., "Analytic queueing network models for parallel processing of task systems," IEEE Transactions on Computers, C-35, 1045, 1986.
· Lukaszewicz, J., "On the estimation of errors introduced by standard assumptions concerning the distribution of activity duration in PERT calculations," Operations Research, 13, 326, 1965.
· Sastry, S., and Parker, A.C., "Stochastic models for wireability analysis of gate arrays," IEEE Transactions on Computer-Aided Design, CAD-5, 1986.
· Kurdahi, F.J., "Techniques for area estimation of VLSI layouts," IEEE Transaction on Computer-Aided Design, 8, 81, 1989.
· Küçükçakar, K., and Parker, A.C., "A methodology and design tools to support system-level VLSI design," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3, 355, 1995.
· Liu, J.W.S., and Liu, C.L., "Performance analysis of multiprocessor systems containing functionally dedicated processors," Acta Informatica, 10, 95, 1978.
· Hwang, J.J., Chow, Y.C., Ahnger, F.D., and Lee, C.Y., "Scheduling precedence graphs in systems with interprocessor communication times," SIAM Journal of Computing, 18, 244, 1989.
· Mouhamed, M., "Lower bound on the number of processors and time for scheduling precedence graphs with communication costs," IEEE Transactions on Software Engineering, 16, 1990.
· Yen, T.-Y., and Wolf, W., "Performance estimation for real-time embedded systems," in Proceedings of the International Conference on Computer Design, 1995, 64.
· Landman, P.E., and Rabaey, J.M., "Activity-sensitive architectural power analysis," IEEE Transactions on CAD, 15, 571, 1996.
· Wadekar, S.A., Parker, A.C., and Ravikumar, C.P., "FREEDOM: Statistical behavioral estimation of system energy and power," in Proceedings of the Eleventh International Conference on VLSI Design, 1998, 30.
· Brand, D., and Visweswariah, C., "Inaccuracies in power estimation during logic synthesis," in Proceedings of the European Design Automation Conference (EURO-DAC), 1996, 388.
· Mehra, R., and Rabaey, J., "Behavioral level power estimation and exploration," in Proceedings of the First International Workshop on Low Power Design, 1994, 197.
· Liu, D., and Svensson, C., "Power consumption estimation in CMOS VLSI chips," IEEE Journal of Solid-State Circuits, 29, 663, 1994.
· Landman, P.E., and Rabaey, J.M., "Activity-sensitive architectural power analysis," IEEE Transactions on Computer-Aided Design, 15, 571, 1996.
· Zeng, B., and Neuvo, Y., "Analysis of floating point roundoff errors using dummy multiplier coefficient sensitivities," IEEE Transactions on Circuits and Systems, 38, 590, 1991.
· Catthoor, F., Vandewalle, J., and De Mann, H., "Simulated annealing based optimization of coefficient and data word lengths in digital filters," International Journal of Circuit Theory Applications, 16, 371, 1988.
· Grzeszczak, A., Mandal, M.K., Panchanathan, S., and Yeap, T., "VLSI implementation of discrete wavelet transform," IEEE Transactions on VLSI Systems, 4, 421, 1996.
· Sung, W., and Kum, Ki-II., "Simulation-based word-length optimization method for fixed-point digital signal processing systems," IEEE Transactions on Signal Processing, 43, 3087, 1995.
"The Infography about System-Level Digital Design Synthesis"
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